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8.7.23 DMA_IEN - Interrupt Enable register
Offset
0x100C
Reset
Access
Name
Bit Position
Bit
31
Name
ERR
Reset
0
Access
RW
Description
DMA Error Interrupt Flag Enable
Set this bit to enable interrupt on AHB bus error.
30:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7
CH7DONE
0
RW
DMA Channel 7 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
6
CH6DONE
0
RW
DMA Channel 6 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
5
CH5DONE
0
RW
DMA Channel 5 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
4
CH4DONE
0
RW
DMA Channel 4 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
3
CH3DONE
0
RW
DMA Channel 3 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
2
CH2DONE
0
RW
DMA Channel 2 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
1
CH1DONE
0
RW
DMA Channel 1 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
0
CH0DONE
0
RW
DMA Channel 0 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
8.7.24 DMA_CHx_CTRL - Channel Control Register
Offset
0x1100
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:22
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
21:16
SOURCESEL
0x00
RW
Source Select
Select input source to DMA channel.
2011-04-12 - d0001_Rev1.10
74
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